Status of the flow for Dominic and Tibor https://indico.mit.edu/event/1505/:
We need to establish a clear tooling plan for full ASIC implementation
Step | Purpose | Tool | Vendor | Approx. Price (Annual) |
---|---|---|---|---|
HLS | C++/SystemC → RTL (Verilog/VHDL) | Catapult HLS | Siemens EDA | TBD (Follow-up needed) |
Logic Synthesis | RTL → Gates | Genus | Cadence | ~$100,000 |
Physical Design | Place & Route (P&R) | Innovus | Cadence | ~$100,000 |
Static Timing Analysis (STA) | Timing sign-off | Innovus | Cadence / Synopsys | / |
Physical Verification | DRC/LVS | Innovus | Cadence / Synopsys | / |
Power Analysis | Power estimation/signoff | Voltus / PrimePower | Cadence / Synopsys | ?? |
Action items:
- Contact Siemens EDA (Catapult pricing & trial)
- Verify Cadence tools access (Genus, Innovus) via MIT (my knowledge is in using Cadence tools, didnt use Synopsys tools before)
- Draft full ASIC flow with tool versions, licenses, costs (we need a tool for simulation and verification, need more detailed sheet on what Catapult does)